Page 117 - Computer_Science_F5

Computer Science Register renaming (b) Write-After-Write (WAW): Two
instructions write to the same register
Modern processors use register renaming
consecutively, where only the second
to optimises instruction execution by
write’s value is needed, making the
abstracting physical registers from
logical registers, increasing instruction-
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level parallelism (ILP) and improving first write redundant.
performance. This technique eliminates Traditional processors employ a two-
bottlenecks caused by multiple instructions operand instruction format, where the
depending on the same physical register. result replaces one of the source operands
By mapping logical registers to a pool (e.g., add r1, r2 updates r1 with r1 + r2).
of physical registers, processors avoid Register renaming, however, adopts
waiting for register availability. Register a three-operand instruction format
renaming eliminates false dependencies, to support independent source and
such as: destination registers. For two-operand
(a) Write-After-Read (WAR): An instructions, like add r1, r2, a temporary
instruction reads a register’s value, register (e.g., r11) is introduced during
and a subsequent instruction writes renaming, transforming it into a three-
to the same register before the value operand instruction internally (e.g., r11
is used, risking outdated data. ← r1 + r2).

Program Example 2.3:

WAR Without Register Renaming

sub r1, r1, r2 // WAR dependency on r1
add r3, r1, r4 // RAW dependency on r1

Program Example 2.4:

WAR With Register Renaming

temp ← r1 - r2 // Rename r1 to a temporary register (eliminates WAR)
add r3, temp, r4 // Add r4 to the saved value from r1 and store in r3

By using a temporary register (temp) for the destination in the first instruction, the
WAR dependency is eliminated. However, as you can see, register renaming does
not solve the RAW dependency since 'add' instruction will still have to wait for the
correct value of temp to be written before reading and adding it to r4.

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Computer Science Form 5.indd 108 23/07/2024 12:33