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like ensuring all the dishes are served
Computer Science given clock cycle. Superscalars still Activity 2.5:
in the correct sequence, even if they
require the compiler to try to schedule
were prepared out of order.
instructions to move dependencies apart
and thereby improve the instruction issue
rate. Even with such compiler scheduling,
FOR ONLINE READING ONLY
difference
important
the
between
superscalars and VLIW processors is Presentation on the benefits of
that the code, whether scheduled by the superscalar execution and ILP in
compiler or not, is guaranteed by the developing imaging applications
hardware to execute correctly. In order You have been selected as part of a
to facilitate dynamic scheduling in team to delevop an image processing
superscalars, the pipeline is divided into application that involves applying
three major units: an instruction fetch multiple filters to an image. By using
and issue unit, multiple functional units reputable materials from the internet
and a commit unit. Dynamic pipeline and library, prepare a presentation to
scheduling leverages the following key show how concepts like superscalar
mechanisms; execution and ILP will benefit the
(a) In-order issue: Instructions are application's performance.
fetched and issued to functional
units in the order they appear in
the program, ensuring program Exercise 2.6
correctness. This is analogous to 1. Consider a program with the
the chefs receiving instructions following instruction sequence:
sequentially from the head chef. Instruction 1: Add A and B,
(b) Out-of-order execution: Once issued, store in C
instructions can be executed out of Instruction 2: Subtract C from
order if no data dependencies exist. D, store in E
This allows the processor to exploit
parallelism by executing instructions Instruction 3: Multiply E and F,
that are ready, even if they arrive store in G
later in the stream. Imagine chefs (a) Explain how a scalar pipelined
working on independent dishes processor would execute this
concurrently, even if they received sequence. How many clock
the recipes at different times. cycles would it likely take
(c) In-order commit: While execution (assuming no pipeline stalls)?
might be out-of-order, the results (b) How would a 2-issue
(written back to memory or registers) superscalar processor
are committed in program order to potentially improve the
maintain program behavior. This is execution time compared to
104
for Advanced Secondary Schools
Computer Science Form 5.indd 104 23/07/2024 12:33
