Page 110 - Computer_Science_F5

Table 2.5: Pipeline with Instruction Level Parallelism (ILP)
Cycles
Instruction 1 2 3 4 5 6 7 8 9
result += a + b IF ID EX MEM WB
FOR ONLINE READING ONLY
result += a + b IF ID EX MEM WB Chapter Two: Performance and optimisation of computer processor
result += a + b IF ID EX MEM WB
result += a + b IF ID EX MEM WB
result += a + b IF ID EX MEM WB
result += a + b IF ID EX MEM WB
result += a + b IF ID EX MEM WB
result += a + b IF ID EX MEM WB
result += a + b IF ID EX MEM WB

result += a + b IF ID EX MEM WB

Data dependence analysis any other), code segment, Instruction
It is important to identify data pipeline diagram(such as graph paper,
dependencies between instructions. If one Microsoft visio, Lucidchart, or other)
instruction relies on the result of another,
they cannot be executed simultaneously. Instructions:
Compilers perform data dependence
analysis to understand these dependencies Step 1: Analyse the code and
and ensure correct execution order even identify dependencies from
when exploiting parallelism. the following generated
MIPS code, assuming all
variables are in memory and
Activity 2.4:
are addressable as offsets
Handling data dependencies in ILP from $t0.

Aim: lw $t1, 0($t0) //Load b to $t1

To understand and optimise instruction- lw $t2, 4($t0) //Load c to $t2
level parallelism by identifying add $t3, $t1,$t2 //$t3 = $t1 + $t2
and mitigating data dependencies,
evaluating the impact of forwarding, and sw $t3, 16($t0) //store $t3 to a
comparing performance improvements. lw $t4, 8($t0) //Load e to $t4
lw $t5, 12($t0) //Load f to $t5
Materials: add $t6, $t4,$t5 //$t6 = $t4 + $t5
Computer with MIPS Simulation
software (such as MARS, SPIM, and sw $t6, 20($t0) //store $t6 to d

101
Student’s Book Form Five

Computer Science Form 5.indd 101 23/07/2024 12:33