Page 107 - Computer_Science_F5

parallelism while maintaining
Computer Science (ii) Loop unrolling: Duplicating the and decode instructions individually.
program correctness.
However, they can analyse these
instructions for potential parallelism
and execute them concurrently on
loop body to expose more potential
parallelism within loops.
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the processor. This approach offers
(iii) Data dependence different execution units within
analysis: Identifying dependencies flexibility compared to VLIW
(potential data hazards) between but might require more complex
instructions to ensure proper hardware to identify parallelism
execution order. opportunities.

Compared to architectures without ILP, Advantages of Instruction-Level
ILP processors generally require simpler Parallelism (ILP)
hardware designs. This is because they (a) Improved performance: ILP
rely on efficient pipelining of instructions can significantly improve the
(breaking down complex operations into performance of processors by
smaller, faster steps) to exploit parallelism. allowing multiple instructions to
Machines without ILP often have more be executed simultaneously. This
intricate hardware dedicated to handling can lead to faster program execution
complex instructions sequentially, making and better system throughput.
them less efficient in terms of exploiting (b) Efficient resource utilisation: ILP can
parallelism. Examples of architectures that help to efficiently utilize processor
exploit ILP are VLIWs and superscalar. resources by allowing multiple
The machines without ILP have complex instructions to be executed at the
hardware which is hard to implement. same time. This can help to reduce
Two prominent architectures leverage resource wastage and increase
ILP effectively: efficiency.
(i) Very Long Instruction Word
(VLIW): These processors pack (c) Reduced instruction dependency:
multiple instructions into a single, ILP can help reduce the number of
wider instruction word. This allows instruction dependencies, which can
them to issue multiple instructions limit the amount of instruction-level
to execution units simultaneously, parallelism that can be exploited. This
maximizing parallelism when can help to improve performance and
possible. reduce bottlenecks.
(ii) Superscalar architecture: Unlike (d) Increased throughput: ILP can help
VLIW, superscalar processors fetch increase the overall throughput of

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Computer Science Form 5.indd 98 23/07/2024 12:33