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Approaches of Instruction Level exist, potentially improving
Parallelism (ILP) efficiency.
(a) Hardware-based approach (iii) Reservation stations: These
(Dynamic) temporary storage locations hold
FOR ONLINE READING ONLY
This approach relies on the processor operands (data) for instructions, Chapter Two: Performance and optimisation of computer processor
hardware itself to discover and exploit enabling faster access during
parallelism dynamically during program execution.
execution. The processor analyses the
instruction stream on the fly, identifying (b) Software-based pproach (Static)
opportunities for parallel execution This approach relies on software tools,
of independent instructions. Since specifically compilers, to identify

the compiler does not need complex parallelism within a program code
analysis to identify parallelism, this during compilation (statically) before the
approach allows for simpler compiler program runs. The compiler analyses the
designs. This approach enhances code code and rearranges instructions to enable
adaptability since hardware can handle parallel execution. This approach yields
variations in program code without higher performance since the compiler
needing code modifications. However, can perform a more thorough analysis
the hardware-based approach presents to uncover parallelism opportunities.
some disadvantages overhead due to Moreover, it gives more control to
hardware analysis which may lead to programmers allowing them to use
lower performance. Also, programmers compiler directives or optimisations to
have less control over how parallelism influence how parallelism is exploited.
is exploited. Examples of processors However, this approach requires complex
that utilise a hardware-based approach compiler design because compilers need
for ILP include Pentium 4 (Intel), AMD
Opteron (AMD), and IBM Power (IBM). sophisticated algorithms to analyse code
for parallelism. It is also presenting less
These processors employ techniques like: adaptability to changing code. Code
(i) Pipelining: Breaking down modifications might require recompiling
instruction execution into stages to optimise for parallelism. Examples
(fetch, decode, execute) allows of processors that utilize software-based
the processor to work on multiple approach for ILP are Itanium 2 (Intel)
instructions simultaneously. processors. Compilers for these processors

(ii) Out-of-order execution: might use techniques like:
Instructions can be reordered for (i) Instruction scheduling: Reordering
execution if no data dependencies instructions to maximize

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Student’s Book Form Five

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