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Computer Science Stalling and forwarding
Stalling
In the previous section, we discovered that pipeline hazards can be resolved by
stalling or forwarding. Recall the previous example of two instructions that cause
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data hazard; add $r1, $r2, $r3 and sub $r4, $r1, $r5. Figure 2.8 shows the pipeline
behaviour. The add instruction does not update register $r1 until the end of stage
5, which occurs at clock cycle 5 (Write back stage). However the sub instruction
needs that value from $r1 at the beginning of stage 2 so that the subtraction can be
executed at clock cycle 4. Therefore, the pipeline must stall, which means staying
idle or doing nothing for two clock cycles until the add instruction updates register
$r1 at clock cycle 5.
Clock cycle
1 2 3 4 5 6 7 8 9 10
add $r1, $r2, $r3 IF ID EX MEM WB
sub $r4, $r1, $r5 IF ID Stall Stall EX MEM WB
Instruction 3 IF ID EX MEM WB
Instruction 4 IF ID EX MEM WB
Figure 2.8: Stalling to resolve a data hazard
Forwarding (a) Hardware modification: The
As we have seen in the previous pipeline is modified to include
example, the pipeline stalls for two hardware for detecting data
cycles to ensure add finishes writing to dependencies and forwarding
r1 before sub reads from it. Forwarding results.
on the other hand involves bypassing (b) Dependency detection: During
the pipeline stages and delivering the the Decode/Execute stage, the
result directly from the source (such processor identifies dependencies
between instructions. For example,
as, ALU output) to the instruction that it recognises that the sub needs the
needs it. Forwarding (bypassing) helps outcome of adding stored in $r1.
the processor to use early results from (c) Forwarding unit: A forwarding
the pipeline to resolve dependencies unit is introduced in the pipeline.
without waiting. This eliminates the This unit checks for dependencies
stall and improves performance. This is and the availability of results from
how forwarding works: previous stages.
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