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Instruction 3 IF ID EX MEM WB Chapter Two: Performance and optimisation of computer processor
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Figure 2.7: Timing diagram for instruction pipeline operation
2. Imagine two MIPS processors with
Exercise 2.1
different pipeline depths: a 5-stage
1. You are analysing a program pipeline (as assumed earlier) and a
running on a MIPS processor with deeper 8-stage pipeline. Discuss the
a 5 stage pipeline. The program potential benefits and drawbacks of
using a deeper pipeline in terms of
has a mix of instructions, with the performance.
following breakdown: add: 40%,
sub: 20%, lw: 20% and sw: 20%.
All instructions take one cycle each Hazards
in the execute stage. Memory access Pipelining aims to improve processor
for lw and sw takes an additional performance by allowing multiple
instructions to be processed simultaneously.
cycle in the Memory Access stage. However, there are situations, called
(a) Assuming a clock cycle time hazards, that prevent the next instruction
of 1 ns (nanosecond), calculate in the instruction stream from executing
the theoretical throughput during its designated clock cycle. Hazards
(instructions completed per reduce the performance from the ideal
second) of this program on a speedup gained by pipelining. There
are three classes of hazards; structural
pipelined processor. hazards, data hazards and control hazards.
(b) How would the throughput
be affected if the program Structural hazards
had a higher percentage of lw These arise from limitations in the
and sw instructions compared hardware. For example, if multiple
to arithmetic instructions? instructions require the same hardware
Explain your reasoning. component (e.g., memory unit) at the
same time, a structural hazard can arise.
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