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Computer Science  circuit for the half adder is illustrated in  From the truth  table,  you obtain  the
           Figure 1.34 which is simplified using the  Boolean  expression for sum (S) and
                                                     carry (C ) as follows:
           XOR gate as shown in Figure 1.35.
                                                             2
            A
                                                                        ABC +
                                                                                ABC
                                                     S =
                                                         ABC +
                                                                ABC +
                       A
                                A . B
                                                                             1
                                                                                     1
                                                                     1
                                                             1
              0 FOR ONLINE READING ONLY
                           B
                          A     A . B     S = A . B + A . B  S =  ABC +  1  ABC +  1  ABC 1 +  ABC 1
           B           B                             S =  C 1 (AB AB+  ) C AB AB+  1 (  +  )
                                 C = A . B           S =  C 1 (AB AB+  ) C AB AB+  1 (  +  )
               Figure 1. 34: Half adder logic circuit  S CA  1 (   ) B   CA 1 (  B )
                   A                                 SC     (A  B )  and C =  AB AC+  +  BC
                                   S = A  ⊕  B            1               2          1    1
                   B
                        A                            The Boolean expressions show that sum
                                   C = A . B         (S) and carry (C) are equivalent to XOR
                                                             A
                        B                            ( S  C   B )  and (C =  2  AB AC+  1  +  BC )
                                                                                         1
                                                          1
             Figure 1. 35: Half adder logic circuit using  gate. The logic circuit for the full adder
                          XOR and AND gates          is illustrated in Figure 1.36.
           Construction of full adder                 A                     S
                                                      B
           A full adder adds three input bits. There   C 1
           are three inputs and two outputs on these
           circuits. The two significant bits to be
           added are represented by two inputs while
           the third input represents the carry from the                               C 2
           previous significant position. Table 1.13
           shows the truth table for the full adder.
                                                      Figure 1.36: Full adder logic circuit using
           Table 1.13: Full adder truth table                    three inputs XOR, OR and three
                   Input             Output                      AND gates
              A     B      C 1   Sum(S)     C 2      The Boolean expression for a carry-out
                    0      0        0        0       (C )  can  be  simplified  using  XOR  as
                                                       2
              0     0      1        1        0       follows:
              0     1      0        1        0       C =  AB AC+    +  BC
              0     1      1        0        1        2           1     1
              1     0      0        1        0       C =  2  AB AC+  1 (B B+  ) BC A A+  1 ( +  )
              1     0      1        0        1       C =  AB AC B ABC+  +   +  AC B BC A+
              1     1      0        0        1        2           1       1     1       1
              1     1      1        1        1       C =  2  AB (1 C+  1  +  C 1 ) AC B BC A+  1  +  1


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     Computer Science Form 5.indd   34                                                      23/07/2024   12:32
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