Page 55 - Computer_Science_F5

Computer Science The block ‘m’ from the main memory can map only to set the number (m mod 3) of
the cache. Within this set, block ‘m’ can map to any available cache line. If all cache
lines are occupied, one of the existing blocks must be replaced.

In the case of fully k-way set mapping, the division of the physical address occurs
FOR ONLINE READING ONLY
as depicted in Figure 1.46.

Tag Set Number Block/Line Offset

Figure 1.46: Physical address of a k-way set associative mapping

Example 1.12

The modern intel 32-bit intel x86 Core i7 processor that is found in many
computers has an 8-way set associative L1 data cache of size 32KB with 64-byte
cache blocks. Calculate the number of bits in the tag, set, and offset fields of a
main memory address.

(a) Number of bits in the physical address is given = 32 as illustrated in Figure
1.47.
32 bits

Tag
Block/Line Offset
Tag Set Number Block/Line Offset
Set Number

Figure 1.47: Number of bits in address
(b) Number of bits in block/line offset
Cache block size given = 64 bytes = 2 6

Number of bits in block offset = 6
32 bits

Tag Set Number Block/Line Offset

6 bits

Figure 1.48: Number of bits in block/line

(c) Number of lines/blocks in the cache
Cachesize 32×2 10
9
Cache lines/blocks = = = 2 blocks/line
Block size 64
(d) Number of sets in the cache

46
for Advanced Secondary Schools

Computer Science Form 5.indd 46 23/07/2024 12:32