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saves its current state (registers, program Interrupt Service Routines (ISRs)
counter) and switches to handling the Each type of interrupt has a corresponding
interrupting event. This context switching Interrupt Service Routine (ISR) that Chapter One: Computer architecture
can introduce slight performance defines the specific actions the processor
takes in response to that interrupt. ISRs are
overhead, but it is essential to ensure typically short code segments that handle
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proper system responsiveness and error the interrupting event and then return
handling. control back to the interrupted program.

Exercise 1.17

1. MIPS utilises the cause and status registers to manage interrupts and exceptions.
Research the specific bit positions and corresponding causes within the Cause
register as seen in Table 1.15 and 1.16. Investigate the status register and its
role in interrupt handling within MIPS ISA. Explain how these registers work
together to differentiate between interrupts and exceptions.

Table 1.15: Codes for MIPS interrupt/exception cause register
Number Name Description
00 INT External Interrupt

01 IBUS Instruction Bus Error (Invalid Instruction)
10 OVF Arithmetic overflow
11 SYSCALL System call

Table 1.16: Mask bits for MIPS Status register

Bit Interrupt/Exception
3 INT
2 IBUS

1 OVF
0 SYSCALL

2. While MIPS utilises polled interrupts, many modern systems employ vectored
interrupt tables. Research the concept of vectored interrupt tables and compare
them to polled interrupts. Discuss the advantages and disadvantages of each
approach. Identify real-world applications where interrupt and exception handling
in MIPS ISA plays a crucial role (such as, device interactions, and system calls).

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Student’s Book Form Five

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